An Out-of-order Superscalar Processor With Speculative Execution And Fast, Precise Interrupts

Publisher Website

24 August 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/micro.1992.697031

Abstract

No abstract available

Keywords

This publication has 8 references indexed in Scilit:

Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers
IEEE Transactions on Computers, 1990
Implementing precise interrupts in pipelined processors
IEEE Transactions on Computers, 1988
Checkpoint Repair for High-Performance Out-of-Order Execution Machines
IEEE Transactions on Computers, 1987
An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors
IEEE Transactions on Computers, 1986
Reducing the cost of branches
ACM SIGARCH Computer Architecture News, 1986
Branch Prediction Strategies and Branch Target Buffer Design
Computer, 1984
Look-Ahead Processors
ACM Computing Surveys, 1975
Detection and Parallel Execution of Independent Instructions
IEEE Transactions on Computers, 1970