On the relationship between yield and cycle time in semiconductor wafer fabrication
- 1 May 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Semiconductor Manufacturing
- Vol. 5 (2) , 156-158
- https://doi.org/10.1109/66.136277
Abstract
No abstract availableThis publication has 3 references indexed in Scilit:
- The use and evaluation of yield models in integrated circuit manufacturingIEEE Transactions on Semiconductor Manufacturing, 1990
- Applying just-in-time in a wafer fab: a case studyIEEE Transactions on Semiconductor Manufacturing, 1989
- Empirical Evaluation of a Queueing Network Model for Semiconductor Wafer FabricationOperations Research, 1988