Virtual-address caches. Part 1: problems and solutions in uniprocessors
- 1 January 1997
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Micro
- Vol. 17 (5) , 64-71
- https://doi.org/10.1109/40.621215
Abstract
In order to support virtual memory, virtual addresses must be efficiently translated into physical addresses. Traditionally, this dynamic translation has been done in a Translation Lookaside Buffer (TLB) before or in parallel with the cache access, so that the cache is indexed and tagged with physical addresses. However, physical-address caches are either slow or limited in size. To solve this bottleneck, caches can be accessed directly with virtual addresses. Unfortunately, consistency problems add complexity to virtual-address caches. These problems are mostly caused by synonyms and address-mapping changes. In this first part, we introduce the problems and discuss solutions in the context of single-processor systems. In Part 2 of this two-part series, we will address multiprocessor issues.Keywords
This publication has 23 references indexed in Scilit:
- Organization And Performance Of A Two-level Virtual-real Cache HierarchyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- On the inclusion properties for multi-level cache hierarchiesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- U-cache: a cost-effective solution to synonym problemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Sharing and protection in a single-address-space operating systemACM Transactions on Computer Systems, 1994
- Evolution of the PowerPC architectureIEEE Micro, 1994
- Eliminating the address translation bottleneck for physical address cachePublished by Association for Computing Machinery (ACM) ,1992
- Introducing the Intel i860 64-bit microprocessorIEEE Micro, 1989
- 801 storage: architecture and programmingACM Transactions on Computer Systems, 1988
- Implementing a cache consistency protocolACM SIGARCH Computer Architecture News, 1985
- Converting a swap-based system to do paging in an architecture lacking page-referenced bitsPublished by Association for Computing Machinery (ACM) ,1981