A 45 K-gate HEMT array with 35-ps DCFL and 50-ps BDCFL gates
- 1 January 1991
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 26 (11) , 1621-1625
- https://doi.org/10.1109/4.98981
Abstract
No abstract availableKeywords
This publication has 6 references indexed in Scilit:
- A high performance GaAs gate array familyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A high density GaAs gate array architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A gigahertz cryogenic HEMT pseudorandom number generator chip setPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- A 40-ps high electron mobility transistor 4.1 K gate arrayIEEE Journal of Solid-State Circuits, 1988
- A Hemt Lsi For A Multibit Data RegisterPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- A high-speed HEMT 1.5K gate arrayIEEE Transactions on Electron Devices, 1987