Subnanosecond emitter-coupled logic gate circuit using Isoplanar II
- 1 October 1973
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 8 (5) , 368-372
- https://doi.org/10.1109/jssc.1973.1050419
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- Epitaxial V-groove bipolar integrated circuit processIEEE Transactions on Electron Devices, 1973
- Oxide isolated ion-implanted bipolar transistors for high packing density and low power-delay productPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1973
- 30-circuit monolithic chip with 750-PS loaded-circuit delay per stagePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1969
- Collector diffusion isolated integrated circuitsProceedings of the IEEE, 1969
- Design and Fabrication of Subnanosecond Current Switch and TransistorsIBM Journal of Research and Development, 1968