A three-dimensional CMOS design methodology

Abstract

A technology-updatable design methodology for three-dimensional CMOS circuits has been developed. Four levels of abstraction have been implemented with topographical congruence: (1) technology level, (2) mask level, (3) transistor level, and (4) logic level. A novel transistor-level symbolic representation is introduced which emphasizes the three-dimensional nature of the circuits. A number of design examples are presented.

Keywords

DESIGN METHODOLOGY
CMOS TECHNOLOGY
ACOUSTICAL ENGINEERING
DESIGN ENGINEERING
INVERTERS
SILICON ON INSULATOR TECHNOLOGY
THIN FILM TRANSISTORS
ISOLATION TECHNOLOGY
LOGIC CIRCUITS
ELECTRICAL ENGINEERING

This publication has 2 references indexed in Scilit:

Stacked transistors CMOS (ST-MOS), an NMOS technology modified to CMOS
IEEE Transactions on Electron Devices, 1982
One-gate-wide CMOS Inverter on laser-recrystallized polysilicon
IEEE Electron Device Letters, 1980