A novel low temperature PVD planarized Al-Cu process for high aspect ratio sub-half micron interconnect
- 24 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 353-356
- https://doi.org/10.1109/iedm.1996.553601
Abstract
A novel low cost and low temperature PVD planarized Al-Cu:0.5% process for simultaneous high aspect ratio interconnect hole fill and metal layer planarization is reported. This is accomplished by using low pressure Al-Cu sputtering deposition with moderate heat applied to the wafers. The low pressure sputtering deposition reduces the amount of migrated Al atoms needed for hole fill and metal layer planarization. The low pressure also helps maintain a very clean environment for easy migration of Al atoms. These features result in excellent interconnect hole fill and metal layer planarization at low temperatures (<450/spl deg/C). Completely filled sub-half micron Al plugs of high aspect ratio (up to 4:1) have been fabricated. Low via resistance (<1.2 /spl Omega/ for 0.35 /spl mu/m vias), high via chain yield (/spl sim/100%), and good via reliability have been demonstrated by this PVD planarized process at a wafer temperature of 380/spl deg/C.Keywords
This publication has 1 reference indexed in Scilit:
- A highly reliable low temperature Al-Cu line/via metallization for sub-half micrometer CMOSIEEE Electron Device Letters, 1995