SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint/recovery
- 1 January 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
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This publication has 31 references indexed in Scilit:
- AR-SMT: a microarchitectural approach to fault tolerance in microprocessorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Cache-aided rollback error recovery (CARER) algorithm for shared-memory multiprocessor systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Speculative versioning cachePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Simics: A full system simulation platformComputer, 2002
- Diskless checkpointingIEEE Transactions on Parallel and Distributed Systems, 1998
- Calculation of the soft error rate of submicron CMOS logic circuitsIEEE Journal of Solid-State Circuits, 1995
- The fuzzy barrier: a mechanism for high speed synchronization of processorsPublished by Association for Computing Machinery (ACM) ,1989
- A case for redundant arrays of inexpensive disks (RAID)Published by Association for Computing Machinery (ACM) ,1988
- Fault-Tolerant Systems in Commercial ApplicationsComputer, 1984
- The Intel 432: A VLSI Architecture for Fault-Tolerant Computer SystemsComputer, 1984