An analog processor architecture for a neural network classifier
- 1 June 1994
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Micro
- Vol. 14 (3) , 16-28
- https://doi.org/10.1109/40.285221
Abstract
Many neural-like algorithms currently under study support classification tasks. Several of these algorithms base their functionality on LVQ-like procedures to find locations of centroids in the data space, and on kernel (or radial-basis) functions centered on these centroids to approximate functions or probability densities. A generic analog chip could implement in a parallel way all basic functions found in these algorithms, permitting construction of a fast, portable classification system.Keywords
This publication has 8 references indexed in Scilit:
- Charge injection in current copier cellsElectronics Letters, 1993
- Regulated cascode switched-current memory cellElectronics Letters, 1990
- On charge injection in analog MOS switches and dummy switch compensation techniquesIEEE Transactions on Circuits and Systems, 1990
- Basic principles of accurate dynamic current mirrorsIEE Proceedings G Circuits, Devices and Systems, 1990
- Self-Organization and Associative MemoryPublished by Springer Nature ,1989
- Current copier cellsElectronics Letters, 1988
- An Algorithm for Vector Quantizer DesignIEEE Transactions on Communications, 1980
- Estimation of a multivariate densityAnnals of the Institute of Statistical Mathematics, 1966