Test generation by fault sampling
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The authors present a novel technique of generating tests from a random sample of faults. The entire fault population of the circuit is randomly divided into two groups. Only one group, usually the smaller one, is used for test generation by the test-generator and fault-simulator programs. This group is known as the sample and its coverage is deterministic. The coverage of faults in the remaining group is similar to that of random vectors and is estimated from the distribution of fault detection probabilities in the circuit. As the sample size increases, the fraction of unsampled faults reduces. At the same time, a larger sample yields more test vectors to increase the random coverage. For a circuit with high testability, a sample of just 5% faults, will provide tests for a 95% coverage. On the other hand, for a circuit with a relatively poor testability, one may have to sample 33% faults for the same coverage. For most practical cases, the sampling approach will mean significant saving in the computation and storage needs of fault simulation.Keywords
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