An Algorithm for the Generation of Test Sets for Combinational Logic Networks
- 1 July 1975
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-24 (7) , 742-746
- https://doi.org/10.1109/t-c.1975.224295
Abstract
An algorithm is developed for generating a single-fault detection test set to be used in a combinational logic network. This algorithm has two unique characteristics. 1) When a test is generated, a list of faults detected by this test is available. Fault simulation, therefore, is not required after the test has been generated. 2) It generates a test set rather than a single test. Each test, with the exception of the first one, is based on a previous test. Repetition of effort and overlapped coverage of faults for different test generations are thus reduced.Keywords
This publication has 3 references indexed in Scilit:
- Algorithms for Detection of Faults in Logic CircuitsIEEE Transactions on Computers, 1971
- Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic CircuitsIEEE Transactions on Electronic Computers, 1967
- Diagnosis of Automata Failures: A Calculus and a MethodIBM Journal of Research and Development, 1966