A novel architecture for reducing the sensitivity of multibit sigma-delta ADCs to DAC nonlinearity
- 19 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 1, 17-20
- https://doi.org/10.1109/iscas.1995.521440
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- An improved sigma-delta modulator architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Multibit sigma-delta modulator with reduced sensitivity to dac nonlinearityElectronics Letters, 1991
- A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversionIEEE Journal of Solid-State Circuits, 1991
- Multibit oversampled Σ-Δ A/D convertor with digital error correctionElectronics Letters, 1988
- The design of sigma-delta modulation analog-to-digital convertersIEEE Journal of Solid-State Circuits, 1988