Facilitating worst-case execution times analysis for optimized code

This publication has 15 references indexed in Scilit:

• Safe and efficient elimination of infeasible execution paths in WCET estimation
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Cache modeling for real-time software: beyond direct mapped instruction caches
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Timing analysis for data caches and set-associative caches
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Automatic derivation of path and loop annotations in object-oriented real-time programs
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Predicting pipelining and caching behaviour of hard real-time programs
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Integrating the timing analysis of pipelining and instruction caching
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• An accurate worst case timing analysis for RISC processors
  IEEE Transactions on Software Engineering, 1995
• Performance analysis of embedded software using implicit path enumeration
  Published by Association for Computing Machinery (ACM) ,1995
• A retargetable technique for predicting execution time of code segments
  Real-Time Systems, 1994
• Predicting program execution times by analyzing static and dynamic program paths
  Real-Time Systems, 1993