The pRAM: an adaptive VLSI chip
- 1 May 1993
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Neural Networks
- Vol. 4 (3) , 408-412
- https://doi.org/10.1109/72.217182
Abstract
The pRAM (probabilistic RAM) is a nonlinear stochastic device with neuron like behavior. The pRAM is realizable in hardware, and the third-generation VLSI pRAM chip is described. This chip is adaptive since learning algorithms have been incorporated on-chip, using reinforcement training. The pRAM chip is also adaptive with respect to the interconnections between neurons. Results achieved from a small net of pRAM's performing a pattern-recognition task using reinforcement training are presentedKeywords
This publication has 4 references indexed in Scilit:
- The application of noisy reward/penalty learning to pyramidal pRAM structuresPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- The noisy-leaky integrator model implemented using pRAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- From Wetware to Hardware: Reverse Engineering Using Probabilistic RAMsJournal of Intelligent Systems, 1992
- Learning probabilistic RAM nets using VLSI structuresIEEE Transactions on Computers, 1992