Inter-task WCET computation for a-way instruction caches
- 1 June 2008
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
In hard real-time applications, Worst Case Execution Time (WCET) is used to check time constraints of the whole system but is only computed at the task level. As most WCET computation methods assume a conservative approach to handle the processor state before the execution of a task, the inter-task analysis of long effect hardware features should improve the accuracy of the result. As an example, we propose to analyze the behavior of an A-way associative instruction cache, by combining inter-and intra-task instruction cache analysis. The aim is to estimate more accurately the number of cache misses due to task chaining by considering task Entry and Exit states along the inter-task analysis. The initial tasks WCETs can be computed by any existing single-task approach that models the instruction cache behavior. A second method is also introduced in this paper which consists in injecting the inter-task cache states in the intra-task WCET analysis, to get more precise numbers.Keywords
This publication has 6 references indexed in Scilit:
- Improving the Worst-Case Execution Time Accuracy by Inter-Task Instruction Cache AnalysisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- Automatic Timing Model Generation by CFG Partitioning and Model CheckingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Component-Wise Instruction-Cache Behavior PredictionPublished by Springer Nature ,2004
- Cache modeling for real-time software: beyond direct mapped instruction cachesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Efficient microarchitecture modeling and path analysis for real-time softwarePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Timing Analysis for Instruction CachesReal-Time Systems, 2000