A 2-Gb/s/pin source synchronous CDMA bus interface with simultaneous multi-chip access and reconfigurable I/O capability

This publication has 4 references indexed in Scilit:

• A 2.7 Gb/s CDMA-interconnect transceiver chip set with multi-level signal data recovery for re-configurable VLSI systems
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• 1.6 Gb/s/pin 4-PAM signaling and circuits for a multi-drop bus
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Concurrency, latency, or system overhead
  Published by Association for Computing Machinery (ACM) ,2001
• A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter
  IEEE Journal of Solid-State Circuits, 1999