Technology scaling and performance limitations in delta-sigma analog-digital converters
- 4 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- Monolithic decimation filtering for custom delta-sigma A/D convertersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A monolithic 20 b delta-sigma A/D converterPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- A fast-settling CMOS op amp with 90 dB DC-gain and 116 MHz unity-gain frequencyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- A 14-bit 80-kHz sigma-delta A/D converter: modeling, design and performance evaluationIEEE Journal of Solid-State Circuits, 1989
- Design Of A Cmos Segond-order Sigma-delta ModulatorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- Performance limitations in switched- capacitor filtersIEEE Transactions on Circuits and Systems, 1985
- MOS ADC-filter combination that does not require precision analog componentsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- Limitations on the performance of field-effect devices for logic applicationsProceedings of the IEEE, 1981
- A unity bit coding method by negative feedbackProceedings of the IEEE, 1963
- A Telemetering System by Code Modulation - Δ- ΣModulationIRE Transactions on Space Electronics and Telemetry, 1962