Capacitance coefficients for VLSI multilevel metallization lines

1 March 1987

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 34 (3) , 644-649
https://doi.org/10.1109/t-ed.1987.22975

Abstract

The problem of reducing the complexity of parasitic capacitance evaluation of interconnection lines in a multilevel stratified dielectric medium (a good approximation for VLSI) is considered. We start out with a review of the Green's function method for the Si-SiO2composite and its derivation via the Fourier integral approach. Next, a piecewise linear finite-element technique is proposed to solve the integral equations that relate charges to potentials and lead to the desired capacitance matrix. We show by example that the proposed method is both less complex than methods based on piecewise constant surface charge distributions and equally accurate. This supports the accuracy and usefulness of the technique for IC design.

Keywords

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