Temporal decomposition for logic optimization
- 15 August 2006
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 8 references indexed in Scilit:
- Dynamic transition relation simplification for bounded property checkingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Managing power and performance for system-on-chip designs using Voltage IslandsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Don't care minimization of multi-level sequential logic networksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Retiming synchronous circuitryAlgorithmica, 1991
- Clock skew optimizationIEEE Transactions on Computers, 1990
- Logic Minimization Algorithms for VLSI SynthesisPublished by Springer Nature ,1984
- Optimizing synchronous systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- A Method for Minimizing the Number of Internal States in Incompletely Specified Sequential NetworksIEEE Transactions on Electronic Computers, 1965