Clock skew optimization
- 1 July 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 39 (7) , 945-951
- https://doi.org/10.1109/12.55696
Abstract
Improving the performance of a synchronous digital system by adjusting the path delays of the clock signal from the central clock source to individual flip-flops is investigated. Using a model to detect clocking hazards, two linear programs are investigated: (1) minimizing the clock period, while avoiding clock hazards, and (2) for a given period, maximizing the minimum safety margin against clock hazard. These programs are solved for a simple example, and circuit simulation is used to contrast the operation of a resulting circuit with the conventionally clocked version. The method is extended to account for clock skew caused by relative variations in the drive capabilities of N-channel versus P-channel transistors in CMOS.Keywords
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