On the comparison of HOL and Boyer-Moore for formal hardware verification
- 1 February 1993
- journal article
- research article
- Published by Springer Nature in Formal Methods in System Design
- Vol. 2 (1) , 45-72
- https://doi.org/10.1007/bf01383943
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- Formal specification and verification of hardware: a comparative case studyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Correctness proofs of parameterized hardware modules in the Cathedral-II synthesis environmentPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A specifier's introduction to formal methodsComputer, 1990
- Automating Recursive Type Definitions in Higher Order LogicPublished by Springer Nature ,1989
- Abstraction Mechanisms for Hardware VerificationPublished by Springer Nature ,1988
- HOL: A Proof Generating System for Higher-Order LogicPublished by Springer Nature ,1988
- Logic programming and digital circuit analysisThe Journal of Logic Programming, 1987