Fault injection boundary scan design for verification of fault tolerant systems

17 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 677-682
https://doi.org/10.1109/test.1994.528013

Abstract

In this paper, we propose a design technique called the Fault Injection Boundary Scan (FIBS) for fault injection that is much more efficient than the traditional hardwired pin-level fault injection. The FIBS augments the boundary scan design to facilitate the injection of faults to the input and output pins of a VLSI chip. In addition to the capabilities of a conventional boundary scan design, the FIBS can interpret the test vector contained in the boundary scan cells as markers for fault-injected pins during fault injection. The compatibility of the FIBS with the boundary scan also promises relatively small overhead.

Keywords

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