Interrupt handling for out-of-order execution processors

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Abstract
Processors with multiple functional units, including the superscalars, achieve significant performance enhancement through low-level execution concurrency. In such processors, multiple instructions are often issued and definitely executed concurrently and out-of-order. Consequently, interrupt and exception handling becomes a vexing problem. The authors identify latency, cost, and performance degradation as factors that must be considered in evaluating the effectiveness of interrupt and exception handling schemes. They then briefly enumerate proposals and implementations for interrupt and exception handling on out-of-order execution processors. An efficient hardware mechanism, the instruction window (IW), and an approach which allows for precise, responsive, and flexible interrupt and exception handling are presented. The implementation of the IW is discussed. The design of an eight-cell IW has been carried out; it can work with a very short machine cycle time. A comparison of all interrupt and exception handling schemes for out-of-order execution processors is also presented.

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