Variable selection in logic synthesis using multiplexers
- 1 September 1980
- journal article
- research article
- Published by Taylor & Francis in International Journal of Electronics
- Vol. 49 (3) , 185-195
- https://doi.org/10.1080/00207218008901165
Abstract
This paper describes a simple algorithm for the design of logic functions using multiplexers. The method relies on the elimination of two or more literals from the set of literals to be connected to the data-select inputs of the multiplexer. Some possible savings in cost using residual gates may be obtained using the same technique.Keywords
This publication has 4 references indexed in Scilit:
- The application of map-entered variables to the use of multiplexers in the synthesis of logic functionsInternational Journal of Electronics, 1978
- Systematic synthesis of combinational circuits using multiplexersElectronics Letters, 1978
- A Decomposition Chart Technique to Aid in Realizations with MultiplexersIEEE Transactions on Computers, 1978
- Algorithm for logic-circuit synthesis by using multiplexersElectronics Letters, 1977