Interconnect Scaling Scenario Using A Chip Level Interconnect Model

Publisher Website

1 January 1997

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 53-54
https://doi.org/10.1109/vlsit.1997.623691

Abstract

No abstract available

Keywords

This publication has 2 references indexed in Scilit:

Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs
IEEE Transactions on Electron Devices, 1993
Optimal interconnection circuits for VLSI
IEEE Transactions on Electron Devices, 1985