A 75-GHz PLL in 90-nm CMOS Technology

1 February 2007

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 01936530,p. 432-613
https://doi.org/10.1109/isscc.2007.373479

Abstract

The design and experimental verification of a 75GHz PLL implemented in a 90nm CMOS process are presented. The circuit incorporates a three-quarter wavelength oscillator and a PFD based on SSB mixers and achieves an operation range of 320MHz and reference sidebands of less than -72dBc while consuming 88mW from a 1.45V supply

Keywords

CMOS TECHNOLOGY
PHASE LOCKED LOOPS
VOLTAGE-CONTROLLED OSCILLATORS
FREQUENCY CONVERSION
PHASE DETECTION
PHASE FREQUENCY DETECTOR
FILTERS
AMPLITUDE MODULATION
MIXERS
INDUCTORS

This publication has 3 references indexed in Scilit:

High-Speed Circuit Designs for Transmitters in Broadband Data Links
IEEE Journal of Solid-State Circuits, 2006
A 40-GHz Frequency Divider in 0.18-$muhboxm$CMOS Technology
IEEE Journal of Solid-State Circuits, 2004
Superharmonic injection-locked frequency dividers
IEEE Journal of Solid-State Circuits, 1999