An accurate analytical delay model for BiCMOS driver circuits
- 1 May 1991
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 10 (5) , 577-588
- https://doi.org/10.1109/43.79495
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- Influence of device parameters on the switching speed of BiCMOS buffersIEEE Journal of Solid-State Circuits, 1989
- A 0.5 μm BiCMOS channelless gate arrayPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- High-speed BiCMOS technology with a buried twin well structureIEEE Transactions on Electron Devices, 1987
- Optimization and scaling of CMOS-bipolar drivers for VLSI interconnectsIEEE Transactions on Electron Devices, 1986