A novel technique for steady state analysis for VLSI circuits in partially depleted SOI
- 21 June 2004
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
This paper presents a computationally efficient technique for accurate analysis of floating-body partially depleted SOI (PD/SOI) CMOS circuits in steady state operating mode. The basic algorithm and techniques to improve the convergence and reduce simulation time are described. The methodology provides over 2 orders of magnitude improvement in simulation time compared with straightforward circuit simulation for large multiple-input circuit macros and SRAMs, thus allowing accurate analysis/assessment of the history effect in PD/SOI CMOS circuits and body voltage and Vt drifts in sensitive circuits.Keywords
This publication has 2 references indexed in Scilit:
- Design considerations of SOI digital CMOS VLSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Controlling floating-body effects for 0.13 μm and 0.10 μm SOI CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002