Systolic architecture for 2-D rank order filtering

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Abstract
The proposed systolic design for 2-D rank order filtering has a wide variety of applications in image processing. It derives its architecture mainly from a systolic design for 1-D rank order filtering proposed previously. The adopted systolic design, called the sample oriented rank order filter design, takes advantage of the evaluated rank values in the current window for the evaluation of the rank values in the next window without explicitly sorting the data in the window. This makes it possible to convert a 2-D windowed data sequence into a 1-D windowed data sequence with multiple data sample exchange at each window movement, and the 1-D systolic design is thus applicable. By cascading many such 1-D systolic arrays into a 2-D array, and supplied with simple parallel-in-serial-out (PISO) logic, this architecture can achieve the maximally available parallelism with nearly 100% efficiency if either the pipeline interleaving or processor sharing technique is used. The design does not require the preloading of the whole 2-D data array, and line scanned images can be processed with negligible time delay.

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