Hardware Verification
- 1 December 1977
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-26 (12) , 1292-1294
- https://doi.org/10.1109/TC.1977.1674795
Abstract
The need for verification of hardware designs is particularly important for large-scale-integration technologies because of the great cost, in time and money, for engineering changes. This correspondence describes an efficient means for determining the equivalence of a behavioral, high-level, i.e., flowchart, definition of the design and a detailed regular logic design. It may be used between compatible high-level as well as low-level designs. A compiler RTRAN transforms the high-level to a low-level design and a program VERIFY determines the equivalence of two such regular logic designs. It seeks to compute a counterexample, starting at the outputs, rather than to try exhaustively input patterns. Experimentally, VERIFY is proven vastly superior to exhaustive simulation. These methods have been used routinely for very large designs.Keywords
This publication has 2 references indexed in Scilit:
- Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional LogicIEEE Transactions on Computers, 1973
- Diagnosis of Automata Failures: A Calculus and a MethodIBM Journal of Research and Development, 1966