Thermal analysis of three-dimensional (3-D) integrated circuits (ICs)

1 January 2001

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 157-159
https://doi.org/10.1109/iitc.2001.930045

Abstract

In this paper, we examine the thermal issues in 3-D ICs by system-level modeling of power dissipation and analytical and numerical modeling of deviceand package-level heat removal. We find that for comparable system performance in 2-D and 3-D ICs, 20%-25% reduction in power dissipation can be achieved by 3-D integration due to lower capacitance associated with interconnects and clock networks. If the system performance in 3-D ICs is higher (compared to that of 2-D ICs), chip temperature could reach an unacceptable level. The chip temperature is generally limited by the heat removal capability of the packaging technology. To reduce the chip temperature in 3-D ICs for reliable operation of devices and interconnects, innovative package-level cooling technologies will be necessary. Thermal vias, Cu bonding layer for 3-D integration, etc. could also be beneficial for heat removal in 3-D ICs.

Keywords

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