A bipolar 2500-gate subnanosecond masterslice LSI
- 1 October 1981
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 16 (5) , 558-562
- https://doi.org/10.1109/jssc.1981.1051637
Abstract
A bipolar 2500-gate subnanosecond masterslice LSI has been developed for use in computer mainframes. A walled-emitter structure has been realized by using double boron ion implantation with an n-type epitaxial layer to obtain high performance and high packing density. A new cell composed of a pair of adjacent gates provides high utilization of input transistors. A gate delay of 0.58 ns with power dissipation of 0.54 mW/gate has been achieved. The masterslice has been applied to an 18-bit memory data register circuit consisting of 1983 internal logic gates and has been mounted on a new 224-pin plug-in package.Keywords
This publication has 5 references indexed in Scilit:
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