Carry time of magnetically coupled Josephson adder circuits
- 1 January 1984
- journal article
- research article
- Published by Wiley in Electronics and Communications in Japan (Part I: Communications)
- Vol. 67 (8) , 117-122
- https://doi.org/10.1002/ecja.4400670814
Abstract
A carry circuit for Josephson adder has been studied and tested experimentally. For carry calculation, a ripple carry process by asymmetrical interferometric majority gates is employed because it can reduce the gate number‐add time products compared with carry look ahead process by conventional OR‐AND gates. Add time measurement has been performed with these carry circuits connected to dummy sum circuits. Operation speed as fast as 740 ps was obtained for 16‐bit calculation, which shows excellent agreement with computer simulation. By the analysis, it has been clarified that the operation speed is limited by impedance mismatched input lines.Keywords
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