A compact, low-power low-jitter digital PLL
- 20 July 2004
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
This paper describes a compact, low-power and low- jitter digital PLL (DPLL). Digitizing the loop filter presents numerous challenges and advantages. In the proposed scheme, a wide-band DPLL is described that achieves low-jitter and low-power consumption. Low- jitter is achieved by using an all-digital adaptive bandwidth control scheme that can track the noise injected into the DPLL and optimise the loop bandwidth accordingly. A prototype DPLL employing has been implemented in a 0.25um CMOS technology. Measurement results show that jitter 130ps jitter is achieved at 144MHz. The area and power consumption outperform the traditional charge-pump based PLL by a factor of 3.5x and 45%, respectively.Keywords
This publication has 3 references indexed in Scilit:
- Low-jitter and process independent DLL and PLL based on self biased techniquesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applicationsIEEE Journal of Solid-State Circuits, 2000
- Low-Power Digital VLSI DesignPublished by Springer Nature ,1995