Redundancies and don't cares in sequential logic synthesis
- 1 February 1990
- journal article
- Published by Springer Nature in Journal of Electronic Testing
- Vol. 1 (1) , 15-30
- https://doi.org/10.1007/bf00134012
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- Easily testable PLA-based finite state machinesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Irredundant sequential machines via optimal logic synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
- A synthesis and optimization procedure for fully and easily testable sequential machinesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- MUSTANG: state assignment of finite state machines targeting multilevel logic implementationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Multi-level logic minimization using implicit don't caresIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Redundancy and Don't Cares in Logic SynthesisIEEE Transactions on Computers, 1983
- An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic CircuitsIEEE Transactions on Computers, 1981
- Diagnosis of Automata Failures: A Calculus and a MethodIBM Journal of Research and Development, 1966
- Minimizing the Number of States in Incompletely Specified Sequential Switching FunctionsIEEE Transactions on Electronic Computers, 1959