A method to generate tests for combinational logic circuits using an ultrahigh-speed logic simulator
- 6 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 102-107
- https://doi.org/10.1109/test.1988.207786
Abstract
We synthesize a test-generation circuit S(C,F) which is a combination of the original combinational circuit C (modified by programmable faults F) and peripheral circuits that automatically generate a test of C. The test pattems are generated by searching the inputs to expose faults at the outputs using an ultrahigh-speed simulator (SP).Keywords
This publication has 8 references indexed in Scilit:
- Test coverage and post-verification defects: A multiple case studyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2009
- On the Acceleration of Test Generation AlgorithmsIEEE Transactions on Computers, 1983
- An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic CircuitsIEEE Transactions on Computers, 1981
- Digital Logic Simulation in a Time-Based, Table-Driven EnvironmentComputer, 1975
- Concurrent simulation of nearly identical digital networksComputer, 1974
- A Deductive Method for Simulating Faults in Logic CircuitsIEEE Transactions on Computers, 1972
- Analyzing Errors with the Boolean DifferenceIEEE Transactions on Computers, 1968
- Diagnosis of Automata Failures: A Calculus and a MethodIBM Journal of Research and Development, 1966