A simple EEPROM cell using twin polysilicon thin film transistors
- 1 August 1994
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 15 (8) , 304-306
- https://doi.org/10.1109/55.296224
Abstract
A planar twin polysilicon thin film transistor (TFT) EEPROM cell fabricated with a simple low temperature (/spl les/600/spl deg/C) process is demonstrated in this work. The gate electrodes of the two TFT's are connected to form the floating gate of the cell, while the source and drain of the larger TFT are connected to form the control gate. The cell is programmed and erased by Fowler-Nordheim tunneling. The threshold voltage of the cell can be shifted by as much as 8 V after programming. This new EEPROM cell can dramatically reduce the cost of production by reducing manufacturing complexity.Keywords
This publication has 3 references indexed in Scilit:
- A novel cell structure for giga-bit EPROMs and flash memories using polysilicon thin film transistorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A Planar Type Eeprom Cell Structure By Standard CMOS Process And ApplicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- Heavy oxynitridation technology for forming highly reliable flash-type EEPROM tunnel oxide filmsElectronics Letters, 1992