Logic simulation with current-limited switches
- 1 January 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 9 (2) , 133-141
- https://doi.org/10.1109/43.46779
Abstract
A switch-level logic simulator for MOS networks based on the theory of current-limited switches is described. It was derived from a switch-level timing simulator by suppressing time-related information and by eliminating invalid events. The simulator obeys Kirchoff's laws and after initialization every node has a known voltage. It can thus be used to drive analog simulation. Fault simulation is easily incorporated by representing the line-open fault by an open circuit and the node-short fault by a short circuit. Examples demonstrate application to both logic and fault simulationKeywords
This publication has 11 references indexed in Scilit:
- Fault modeling for MOS digital circuits using current limited switchPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Current-limited switch-level timing simulator for MOS logic networksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- A Multivalued Algebra For Modeling Physical Failures in MOS VLSI CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- Relaxation-Based Electrical SimulationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1984
- Fault Modeling for Digital MOS Integrated CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1984
- A Switch-Level Model and Simulator for MOS Digital SystemsIEEE Transactions on Computers, 1984
- Cascode voltage switch logic: A differential CMOS logic familyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- A unified switching theory with applications to VLSI designProceedings of the IEEE, 1982
- Techniques for the simulation of large-scale integrated circuitsIEEE Transactions on Circuits and Systems, 1979
- MOTIS-An MOS timing simulatorIEEE Transactions on Circuits and Systems, 1975