A CMOS signed multiplier using wave pipelining
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 12.3.1-12.3.4
- https://doi.org/10.1109/cicc.1993.590699
Abstract
The authors present a high-performance 8 /spl times/ 8 CMOS signed multiplier using the wave pipelining technique. The multiplier architecture is based on the modified Booth algorithm and Wallace-Tree techniques. At the transistor level, a biased CMOS gate is used to balance the path delays; it provides a means of postprocess tuning, even though it has a disadvantage in power consumption. The multiplier is implemented with MOSIS 2-/spl mu/m technology, and simulation results show a tenfold speed-up over nonpipelined operation.Keywords
This publication has 4 references indexed in Scilit:
- A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technologyIEEE Journal of Solid-State Circuits, 1991
- Method to reduce the sign bit extension in a multiplier that uses the modified Booth algorithmElectronics Letters, 1986
- A Suggestion for a Fast MultiplierIEEE Transactions on Electronic Computers, 1964
- A SIGNED BINARY MULTIPLICATION TECHNIQUEThe Quarterly Journal of Mechanics and Applied Mathematics, 1951