Exact evaluation of memory size for multi-dimensional signal processing systems
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Memory cost is typically responsible for up to 80% of the chip and/or board area of most video and image processing system realizations. We present a novel technique - founded on data-flow analysis - which allows us to address the problem of background memory size evolution for a given nonprocedural algorithm specification. Usually, the number of signal instances is huge, so a new data-flow model grouping scalar signals in so-called basic sets is proposed. The method also incorporates a way to trade-off memory size with computational and controller complexity.Keywords
This publication has 6 references indexed in Scilit:
- Post-processor for data path synthesis using multiport memoriesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- PHIDEO: a silicon compiler for high speed algorithmsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- TRANSFORMATION OF NESTED LOOPS WITH MODULO INDEXING TO AFFINE RECURRENCESParallel Processing Letters, 1994
- An area model for on-chip memories and its applicationIEEE Journal of Solid-State Circuits, 1991
- REAL: a program for REgister ALlocationPublished by Association for Computing Machinery (ACM) ,1987
- Fourier-Motzkin elimination and its dualJournal of Combinatorial Theory, Series A, 1973