A 4 Gsamples/s line-receiver in 0.8 μm CMOS

Publisher Website

23 December 2002

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 116-117
https://doi.org/10.1109/vlsic.1996.507736

Abstract

No abstract available

Keywords

This publication has 3 references indexed in Scilit:

A 1.5 GHz highly linear CMOS downconversion mixer
IEEE Journal of Solid-State Circuits, 1995
A monolithic 480 Mb/s parallel AGG/decision/clock-recovery circuit in 1.2- mu m CMOS
IEEE Journal of Solid-State Circuits, 1993
A variable delay line PLL for CPU-coprocessor synchronization
IEEE Journal of Solid-State Circuits, 1988