C-MOS/SOS gate-protection networks
- 1 August 1978
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 25 (8) , 917-925
- https://doi.org/10.1109/t-ed.1978.19202
Abstract
To protect C-MOS/SOS LSI circuits from electrostatic discharge and resulting dielectric breakdown of the gate insulator, various gate-protection networks are employed. This paper reports on the evaluation of high-voltage diodes, Zener diodes, distributed diode-resistor combinations, and spark-gap devices for use in gate protection network applications. Results of pulse-power burnout, current-voltage (dc) characterization, bias-temperature stress, and radiation effects on individual test devices are analyzed to provide guidelines for protection, circuit selection, and design.This publication has 11 references indexed in Scilit:
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