A scalable architecture for 2-D discrete wavelet transform
- 23 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
We propose an efficient and simple systolic-like architecture for VLSI implementation of a 2-D discrete wavelet transform (DWT). The "approximation" and "detailed" components of a signal are computed simultaneously in the first octave and alternately in the other octave(s). Each processing element has its own local memory for storing intermediate data and minimum routing requirement limited only to its neighbors. The proposed architecture uses the same clock frequency for every octave level and has a 100% utilization for j=2 architecture, and N/sup 2/+N period cycle. The architecture is scalable for different filter lengths (divisible by 2) and different octave levels.Keywords
This publication has 6 references indexed in Scilit:
- Distributed memory and control VLSI architectures for the 1-D Discrete Wavelet TransformPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A scalable systolic array architecture for 2D discrete wavelet transformsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- VLSI architectures for discrete wavelet transformsIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1993
- VLSI architecture for 2-D Daubechies wavelet transform without multipliersElectronics Letters, 1991
- VLSI architecture for the discrete wavelet transformElectronics Letters, 1990
- Multifrequency channel decompositions of images and wavelet modelsIEEE Transactions on Acoustics, Speech, and Signal Processing, 1989