Motivation for Variable Length Intervals and Hierarchical Phase Behavior
- 1 January 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Most programs are repetitive, where similar behavior can be seen at different execution times. Proposed algorithms automatically group similar portions of a program's execution into phases, where the intervals in each phase have homogeneous behavior and similar resource requirements. These prior techniques focus on fixed length intervals (such as a hundred million instructions) to find phase behavior. Fixed length intervals can make a program's periodic phase behavior difficult to find, because the fixed interval length can be out of sync with the period of the program's actual phase behavior. In addition, a fixed interval length can only express one level of phase behavior. In this paper, we graphically show that there exists a hierarchy of phase behavior in programs and motivate the need for variable length intervals. We describe the changes applied to SimPoint to support variable length intervals. We finally conclude by providing an initial study into using variable length intervals to guide SimPointKeywords
This publication has 26 references indexed in Scilit:
- Transition Phase Classification and PredictionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Phase-Aware Remote ProfilingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- EXPERTPublished by Association for Computing Machinery (ACM) ,2004
- Structures for phase classificationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Runtime power monitoring in high-end processors: methodology and empirical dataPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Positional adaptation of processors: application to energy reductionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- How to use SimPoint to pick simulation pointsACM SIGMETRICS Performance Evaluation Review, 2004
- Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core ArchitecturesIEEE Computer Architecture Letters, 2003
- An architectural framework for runtime optimizationIEEE Transactions on Computers, 2001
- Whole program pathsPublished by Association for Computing Machinery (ACM) ,1999