Power-constrained microprocessor design

26 June 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 14-16
https://doi.org/10.1109/iccd.2002.1106740

Abstract

Power dissipation and power density have become first-order design constraints, even for high-performance systems. For future designs it will be the dominant constraint. In this paper we suggest a systematic approach to optimizing a processor design under (only) a power constraint. The approach uses the energy-performance ratio (EPR) of the various design parameters as the key to identifying opportunities for improving energy-efficiency.

Keywords

MICROPROCESSORS
PARAMAGNETIC RESONANCE
ENERGY EFFICIENCY
PIPELINE PROCESSING
CONSTRAINT OPTIMIZATION
CLOCKS
COSTS
MICROELECTRONICS
POWER DISSIPATION
DESIGN OPTIMIZATION

This publication has 2 references indexed in Scilit:

Towards an energy complexity of computation
Information Processing Letters, 2001
Energy dissipation in general purpose microprocessors
IEEE Journal of Solid-State Circuits, 1996