An FPGA based Walsh Hadamard transforms
- 13 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 2, 569-572
- https://doi.org/10.1109/iscas.2001.921134
Abstract
The Walsh-Hadamard transforms are important in many image processing applications including compression, filtering and code design. This paper presents a novel architecture for the fast Hadamard transform, using distributed arithmetic techniques. The mathematical model for the algorithm proposed, the associated design using both a distributed arithmetic ROM and accumulator structure and a sparse matrix factorisation technique, together with the implementation of the algorithm on a Xilinx FPGA board are described. The design has O(2n) computation time complexity, where n is the input data wordlength, requires less area when compared with existing systolic architectures and is suitable for FPGA implementations.Keywords
This publication has 7 references indexed in Scilit:
- A high throughput FPGA implementation of a bit-level matrix-matrix productPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Family of unified complex Hadamard transformsIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1999
- New distributed arithmetic algorithm and its application to IDCTIEE Proceedings - Circuits, Devices and Systems, 1999
- A modular approach to the computation of convolution sum using distributed arithmetic principlesIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1999
- Hadamard transforms on multiply/add architecturesIEEE Transactions on Signal Processing, 1994
- A bit level systolic array for Walsh-Hadamard transformsSignal Processing, 1993
- Fast Hadamard transform based on a simple matrix factorizationIEEE Transactions on Acoustics, Speech, and Signal Processing, 1986