An Advanced, Radiation Hardened Bulk CMOS/LSI Technology

1 January 1981

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science

Vol. 28 (6) , 4033-4037
https://doi.org/10.1109/tns.1981.4335669

Abstract

An advanced, second generation, bulk, Si-gate CMOS process is described. This process is capable of producing LSI and VLSI parts that are latch-up free and hardened to total dose levels in excess of 2 × 105 rad-Si for applications in space and weapons radiation environments. Two memories designed to use this process are also described. Both circuits are 4096-bit, static CMOS RAMs.

Keywords

CMOS TECHNOLOGY
RADIATION HARDENING
LARGE SCALE INTEGRATION
OXIDATION
CMOS PROCESS
GEOMETRY
RANDOM ACCESS MEMORY
CIRCUITS
IMPLANTS
STRIPS

This publication has 2 references indexed in Scilit:

Inverter Hardness Predictions and Correlation with LSI Device Failure Doses
IEEE Transactions on Nuclear Science, 1980
Latch-Up Elimination in Bulk CMOS LSI Circuits
IEEE Transactions on Nuclear Science, 1980