A parallel ASIC VLSI neurocomputer for a large number of neurons and billion connections per second speed
- 1 January 1991
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 2, 2162-2167 vol.3
- https://doi.org/10.1109/ijcnn.1991.170708
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- A VLSI architecture for high-performance, low-cost, on-chip learningPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- An artificial neural network accelerator using general purpose 24 bit floating point digital signal processorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- Neural network simulation at Warp speed: how we got 17 million connections per secondPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- Parallel Distributed ProcessingPublished by MIT Press ,1986