The Damage Susceptibility of Integrated Circuits to a Simulated IEMP Transient

Abstract
Recent investigations have been directed toward gaining insight into the effect of electrical pulse overstressing in integrated circuits, especially simple gates and bipolar LSI arrays. In order to determine the effect of ionizing radiation on the pulse-power failure susceptibility levels of small scale, monolithic, junction-isolated integrated circuits (simple gates), an experimental study was undertaken such that device failures could be induced in a simulated EMP or IEMP environment. The device types investigated included low- and high-power, quadruple, dual-input, positive NAND TTL gates. Permanent damage levels for these devices were determined for both positive and negative-polarity sub-microsecond pulses, introduced into the input, output and bias terminals of active devices, some of which were simultaneously irradiated by gamma radiation. The radiation dose rates ranged from 1 × 1010 to 5 × 1010 rads(Si)/sec. The failure susceptibility level of a device was found to depend uniquely upon the ionizing radiation, the device terminal subjected to the electrical stress pulse, and the polarity of the pulse. The data for device failures in the simulated EMP environment agree with the existing thermal-failure models characterized by P = Atm, where P is the power required to induce failure and t is the time to failure. In a radiation environment it was observed that initial ionization tends to reduce the magnitude of the constant A and shifts the time to failure t from the constant-energy regime (m = -1) to another.

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