An NMOS voltage reference
- 1 January 1978
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
An NMOS temperature-stable voltage reference, affording - in breadboard results - a temperature drift of less than 6 PPM/°C, will be described. Calculations show that less than 2 PPM/°C can be achieved with proper choice of device geometries.Keywords
This publication has 2 references indexed in Scilit:
- Double boron implant short-channel MOSFETIEEE Transactions on Electron Devices, 1977
- Modeling of an ion-implanted silicon-gate depletion-mode IGFETIEEE Transactions on Electron Devices, 1975